This disclosure pertains to the field of clock and data recovery in a communication channel.
A communication system 100, as shown in FIG. 1, includes a transmitter (TX), transmission medium or channel, and a receiver (RX). The transmitter transmits digitally encoded data through the communication channel, which introduces inter-symbol interference to the transmitted data at the channel output. The receiver processes the channel output using an “equalizer” to mitigate the effects of the inter-symbol interference. The receiver also samples the channel output at particular time instances to properly detect (e.g., slice) the received data without error. Examples of communication channels include read channels for data storage, high speed serial links, deep space satellite communication channels etc. The high speed serial link used in the NVLINK technology developed by nVIDIA Corporation is another example.
Equalizers in the receiver are used to mitigate the effects of inter-symbol interference. Examples of equalizers are the continuous time linear equalizer (CTLE), the sampled data finite impulse response (FIR) filter (also known as a receiver feed forward equalizer (FFE)), and the decision feedback equalizer (DFE). One or more of these equalizers may be optionally used in a receiver implementation.
A data detector at the receiver generates detected data bits or symbols. An example of a data detector is a simple latch or data slicer, which slices a voltage at a programmable threshold. Another example of a data detector is an analog to digital converter (ADC), which produces a multi-bit output from which the data may be detected and from which an estimate of the error in the detected data may also be computed. Another example of a (more complex) data detector is a maximum-likelihood sequence detector (also known as a Viterbi detector). A Viterbi detector is typically used in conjunction with a preceding analog to digital converter stage.
In addition to mitigating the effects of inter-symbol interference or other impairments, the receiver must use a clock and data recovery system to sample the signal at a desirable sampling phase before the sampled data is detected using the data detector. A typical clock and data recovery is a feedback or control system and includes three key components:
(1) a phase detector to convert received amplitude information to an estimate of the error in sampling time and phase present at the current sampling interval;
(2) a loop filter that filters unwanted noise and jitter present in the phase detector estimate; and
(3) a timing adjustment mechanism such that the loop filter output adjusts the sampling phase of the receiver.
Examples of timing adjustment elements are phase interpolators, voltage controlled oscillators (VCOs), phase mixers, or some combination of these example elements.
The phase detector may also be referred to as a gradient calculator, and is typically deployed to drive the clock and data recovery control loop. The phase detector may be an oversampled phase detector such a bang-bang or Alexander phase detector, or a baud rate phase detector. An oversampled phase detector uses additional sampled data to supplement the main clock and data recovery sampled data. For example, a typical bang-bang phase detector uses data sampled at 0.5 unit intervals offset from the data obtained from the clock and data recovery. In contrast, a baud rate phase detector uses only the data obtained from the clock and data recovery.